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cwy?|?`p<_?o?vv?pcbbsh7n[?? this document is a general product description and is subject to change without notice. hynix does not assume any responsibility for use of circuits described. no patent licenses are im plied. rev 1.2 / july. 2009 1 256mbit mobile ddr sdram based on 4m x 4bank x16 i /o specification of 256mb (16mx16bit) mobile ddr sdram memory cell array - organized as 4banks of 4,194,304 x16
this document is a general product description and is subject to change without notice. hynix does not assume any responsibility for use of circuits described. no patent licenses are im plied. rev 1.2 / july. 2009 2 256mbit mobile ddr sdram based on 4m x 4bank x16 i /o document title 256mbit (4bank x 4m x 16bits) mobile ddr sdram revision history revision no. history draft date remark 0.1 - initial draft may 2008 preliminary 0.2 - idd specification updated may 2008 preliminary 1.0 - the final version nov. 2008 1.1 - insert ddr370 dc/ac characteristics apr. 2009 1.2 - omit a typo in package information july. 2009
rev 1.2 / july. 2009 3 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series features summary mobile ddr sdram - double data rate architecture: two data transfer per clock cycle mobile ddr sdram interface - x16 bus width - multiplexed address (row address and column ad- dress) supply voltage - 1.8v device: vdd and vddq = 1.7v to 1.95v memory cell array - 256mbit (x16 device) = 4m x 4bank x 16 i/o data strobe - x16 device: ldqs and udqs - bidirectional, data strobe (dqs) is transmitted and re- ceived with data, to be used in capturing data at t he receiver - data and data mask referenced to both edges of d qs low power features - pasr (partial array self refresh) - auto tcsr (temperature compensated self refresh) - ds (drive strength) - dpd (deep power down): dpd is an optional featur e, so please contact hynix office for the d pd feature input clock - differential clock inputs (ck, ck ) data mask - ldm and udm: input mask signals for write data - dm masks write data-in at the both rising and falling edges of the data strobe mode rerister set, extended mode regis- ter set and status register read - keep to the jedec standard regulation (low power ddr sdram) cas latency - programmable cas latency 2 or 3 supported burst length - programmable burst length 2 / 4 / 8 with both se quen- tial and interleave mode auto precharge - option for each burst access auto refresh and self refresh mode clock stop mode - clock stop mode is a feature supported by mobile ddr sdram. - keep to the jedec standard regulation initializing the mobile ddr sdram - occurring at device power up or interruption of device power package - h5ms2562jfr: 60 ball fbga, lead & halogen free this product is in compliance with the directive pertaining of rohs.
rev 1.2 / july. 2009 4 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series description the hynix h5ms2562jfr series is 268,435,456-bit cmo s low power double data rate synchronous dram (mobi le ddr sdram), ideally suited for mobile applications which use the battery such as pdas, 2.5g and 3g cel lular phones with internet access and multimedia capabilities, m ini-notebook, hand-held pcs. it is organized as 4ba nks of 4,194,304 x16. the hynix h5ms2562jfr series uses a double-data-rat e architecture to achieve high-speed operation. the double data rate architecture is essentially a 2 n prefetch architecture with an interface designed t o transfer two data per clock cycle at the i/o pins. the hynix h5ms2562jfr series offers fully synchrono us operations referenced to both rising and falling edges of the clock. while all address and control inputs are lat ched on the rising edges of the ck (mobile ddr sdra m operates from a differential clock : the crossing of ck going high and ck going low is referred to as the positive edge of c k ), data, data strobe and data mask inputs are sampled on both rising and falling edges of it ( input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck ). the data paths are internally pipelined and 2-bit prefetched to achieve high bandwidth. all input voltage level s are compatible with lvcmos. read and write accesses to the low power ddr sdram (mobile ddr sdram) are burst oriented; accesses sta rt at a selected location and continue for a programmed num ber of locations in a programmed sequence. accesses begin with the registration of an active command, which is the n followed by a read or write command. the address bits reg- istered coincident with the active command are used to select the bank and the row to be accessed. the address bits registered coincident with the read or write comman d are used to select the bank and the starting colu mn location for the burst access. the low power ddr sdram (mobile ddr sdram) provides for programmable read or write bursts of 2, 4 or 8 loca- tions. an auto precharge function may be enabled to provide a self-timed row precharge that is initiat ed at the end of the burst access. as with standard sdram, the pipelined and multibank architecture of low power ddr sdram (mobile ddr sd ram) allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge an d activation times. the low power ddr sdram (mobile ddr sdram) also pro vides for special programmable self refresh options which are partial array self refresh (full, half, quarter and 1/8 and 1/16 array) and temperature compensate d self refresh. a burst of read or write cycles in progress can be interrupted and replaced by a new burst read or wri te command on any cycle (this pipelined design is not restricted by a 2n rule). only read bursts in progress with au to precharge disa- bled can be terminated by a burst terminate command . burst terminate command is undefined and should n ot be used for read with autoprecharge enabled and for wr ite bursts.
rev 1.2 / july. 2009 5 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series the hynix h5ms2562jfr series has the special low po wer function of auto tcsr (temperature compensated self refresh) to reduce self refresh current consumption . since an internal temperature sensor is implement ed, it enables to automatically adjust refresh rate according to t emperature without external emrs command. deep power down mode is an additional operating mod e for low power ddr sdram (mobile ddr sdram). this mode can achieve maximum power reduction by removing pow er to the memory array within low power ddr sdram (mobile ddr sdram). by using this feature, the syst em can cut off almost all dram power without adding the cost of a power switch and giving up mother-board power-lin e layout flexibility. all inputs are lvcmos compatible. devices will have a v dd and v ddq supply of 1.8v (nominal). the hynix h5ms2562jfr series is available in the fo llowing package: - 60ball fbga [8mm x 10mm, t=1.0mm max ] 256mb mobile ddr sdram ordering information part number clock frequency organiza- tion interface operating temperature package H5MS2562JFR-E3M 200mhz(cl3) / 83mhz(cl2) 4banks x 4mb x 16 lvcmos mobile temp (-30 o c ~ 85 o c) lead & halogen free h5ms2562jfr-j3m 166mhz(cl3) / 83mhz(cl2) h5ms2562jfr-k3m 133mhz(cl3) / 83mhz(cl2) h5ms2562jfr-l3m 100mhz(cl3) / 66mhz(cl2)
rev 1.2 / july. 2009 6 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series information for hynix known good die with the advent of multi-chip package (mcp), packag e on package (pop) and system in a package (sip) ap plications, customer demand for known good die (kgd) has increa sed. requirements for smaller form factors and higher me mory densities are fueling the need for wafer-level memory solu- tions due to their superior flexibility. hynix know n good die (kgd) products can be used in packaging technologies such as systems-in-a-package (sip) and multi-chip p ackage (mcp) to reduce the board area required, mak ing them ideal for hand-held pcs, and many other portable di gital applications. hynix mobile sdram will be able to continue its con stant effort of enabling the advanced package produ cts of all appli- cation customers. - please contact hynix office for hynix kgd product availability and informations.
rev 1.2 / july. 2009 7 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series 60ball fbga assignment vss vddq vssq vddq vssq vss cke a9 dq15 dq13 dq11 dq9 udqs udm ck a11 ab c d e f gh a6 a7 j vss a4 k vssq dq14 dq12 dq10 dq8 nc /ck a12 a8 a5 vddq dq1 dq3 dq5 dq7 nc /we /cs a10 a2 dq0 dq2 dq4 dq6 ldqs ldm /cas ba0 a0 a3 vdd vssq vddq vssq vddq vdd /ras ba1 a1 vdd 1 2 3 4 5 6 7 8 9 top view
rev 1.2 / july. 2009 8 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series mobile ddr sdram pin descriptions symbol type description ck, ck input clock: ck and ck are differential clock inputs. all address and con trol input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck (both directions of crossing). cke input clock enable: cke high activates, and cke low deact ivates internal clock signals, device input buffers and output drivers. taking cke low pr ovides precharge power-down and self refresh operation (all banks idle), or act ive power-down (row active in any bank). cke is synchronous for all functions exc ept for self refresh exit, which is achieved asynchronously. cs input chip select: cs enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered ba0, ba1 input bank address inputs: ba0 and ba1 define to which ba nk an active, read, write or precharge command is being applied. ba0 and ba1 als o determine which mode register is to be loaded during a mode register set command (mrs, emrs or srr). a0 ~ a12 input address inputs: provide the row address for active commands, and the column address and auto precharge bit for read/write commands, to select one location out of the memory array in the respective bank. the address in puts also provide the op-code during a mode register set command. a10 sampled during a p recharge command deter- mines whether the precharge applies to one bank (a1 0 low) or all banks (a10 high). if only one bank is to be precharged, the bank is s elected by ba0, ba1. for 256mb (x16), row address: a0 ~ a12, column addr ess: a0 ~ a8 auto-precharge flag: a10 dq0 ~ dq15 i/o data bus: data input / output pin ldm ~ udm input input data mask: dm is an input mask signal for wri te data. input data is masked when dm is sampled. high along with that input data duri ng a write access. dm is sampled on both edges of dqs. data mask pins include dummy loading internally, to match the dq and dqs loading. for x16 devices, ldm corresponds to the data on dq0 -dq7, and udm corresponds to the data on dq8-dq15. ldqs ~ udqs i/o data strobe: output with read data, input with writ e data. edge-aligned with read data, center-aligned with write data. used to capture wri te data. for x16 device, ldqs corresponds to the data on dq0 -dq7, and udqs corresponds to the data on dq8-dq15. v dd supply power supply v ss supply ground v ddq supply i/o power supply v ssq supply i/o ground nc - no connect: no internal electrical connection is present.
rev 1.2 / july. 2009 9 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series functional block diagram 4mbit x 4banks x 16 i/o mobile ddr sdram 16 sense amp & i/o gate output buffer & logic address register mode register state machine address buffers bank select row active cas latency clk cke /cs /ras /cas /we ldm ~udm a0 a1 ba1 ba0 a12 pasr refresh dq0 dq15 row decoders row decoders row decoders row decoders column decoders 4mx16 bank0 4mx16 bank1 4mx16 bank2 4mx16 bank3 memory cell array data out control burst length /clk input buffer & logic ds 32 16 32 data strobe transmitter data strobe receiver ds ldqs ~ udqs extended mode register self refresh logic & timer internal row counter write data register 2-bit prefetch unit row pre decoder column pre decoder column add counter burst counter column active
rev 1.2 / july. 2009 10 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series register definition i mode register set (mrs) for mobile ddr sdram ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 0 0 0 0 0 0 cas latency bt burst length burst type a3 burst type 0 sequential 1 interleave burst length a2 a1 a0 burst length a3 = 0 a3=1 0 0 0 reserved reserved 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 reserved reserved cas latency a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved
rev 1.2 / july. 2009 11 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series register definition ii extended mode register set (emrs) for mobile ddr sd ram ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 1 0 0 0 0 0 0 0 ds 0 0 pasr pasr (partial array self refresh) a2 a1 a0 self refresh coverage 0 0 0 all banks (default) 0 0 1 half of total bank (ba1=0) 0 1 0 quarter of total bank (ba1=ba0=0) 0 1 1 reserved 1 0 0 reserved 1 0 1 one eighth of total bank (ba1 = ba0 = row address msb=0) 1 1 0 one sixteenth of total bank (ba1 = ba0 = row address 2 msbs=0) 1 1 1 reserved ds (drive strength) a7 a6 a5 drive strength 0 0 0 full 0 0 1 half (default) 0 1 0 quarter 0 1 1 octant 1 0 0 three-quarters
rev 1.2 / july. 2009 12 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series register definition iii status register (sr) for mobile ddr sdram note) 1. the revision number starts at 0000 and increme nts by 0001 each time a change in the manufacturer s specification, ibis, or process occurs. 2. low temperature out of range. 3. high temperature out of range - no refresh rate ca n guarantee functionality. 4. the refresh rate multiplier is based on the memor ys temperature sensor. 5. required average periodic refresh interval = tref i * multiplier. 6. status register is only for read. 7. to read out status register values, ba[1:0] set to 01b and a[12:0] set to all 0 with mrs command fol lowed by read command with that ba[1:0] and a[12:0] are dont care. ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 dq15 dq14 dq13 dq12 dq11 dq10 dq9 dq8 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 density - dw refresh rate revision identification manufa cturers identification 0 0 1 0 0 x x x x 1) x 1) x 1) x 1) 0 1 1 0 density dq15 dq14 dq13 density 0 0 0 128 0 0 1 256 0 1 0 512 0 1 1 1024 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved dw (device width) dq11 device width 0 16 bits 1 32 bits refresh rate dq10 dq9 dq8 refresh rate 0 0 x 4 2) 0 1 0 4 0 1 1 2 1 0 0 1 1 0 1 0.5 1 1 0 0.25 1 1 1 0.25 3) manufacturers identification dq3 dq2 dq1 dq0 manufacturer 0 1 1 0 hynix x x x x reserved or other companies
rev 1.2 / july. 2009 13 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series command truth table dm truth table note: 1. all states and sequences not shown are illegal o r reserved. 2. deslect and nop are functionally interchangeable. 3. autoprecharge is non-persistent. a10 high enable s autoprecharge, while a10 low disables autoprechar ge 4. burst terminate applies to only read bursts with auto precharge disabled. this command is undefined and should not be used for read with autoprecharge enabled, and for write burs ts. 5. this command is burst terminate if cke is high an d deep power down entry if cke is low. 6. if a10 is low, bank address determines which bank is to be precharged. if a10 is high, all banks are precharged and ba0-ba1 are don ' t care. 7. this command is auto refresh if cke is high, and self refresh if cke is low. 8. all address inputs and i/o are '' don ' t care '' except for cke. internal refresh counters control ba nk and row addressing. 9. all banks must be precharged before issuing an au to-refresh or self refresh command. 10. ba0 and ba1 value select among mrs, emrs and sr r. 11. used to mask write data, provided coincident wi th the corresponding data. 12. cke is high for all commands shown except self r efresh and deep power-down. function cs ras cas we ba a10/ap addr note deselect (nop) h x x x x x x 2 no operation (nop) l h h h x x x 2 active (select bank and activate row) l l h h v row row read (select bank and column and start read burst) l h l h v l col read with ap (read burst with autoprecharge) l h l h v h c ol 3 write (select bank and column and start write burst) l h l l v l col write with ap (write burst with autoprecharge) l h l l v h col 3 burst terminate or enter deep power down l h h l x x x 4, 5 precharge (deactivate row in selected bank) l l h l v l x 6 precharge all (deactivate rows in all banks) l l h l x h x 6 auto refresh or enter self refresh l l l h x x x 7,8,9 mode register set l l l l v op code 10 function dm dq note write enable l valid 11 write inhibit h x 11
rev 1.2 / july. 2009 14 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series cke truth table note: 1. cken is the logic state of cke at clock edge n ; cke n -1 was the state of cke at the previous clock edge. 2. current state is the state of lp ddr immediately prior to clock edge n . 3. command n is the command registered at clock edge n, and act ion n is the result of command n . 4. all states and sequences not shown are illegal o r reserved. 5. deselect and nop are functionally interchangeable . 6. power down exit time (t xp ) should elapse before a command other than nop or d eselect is issued. 7. self refresh exit time (t xsr ) should elapse before a command other than nop or deselect is issued. 8. the deep power-down exit procedure must be follow ed as discussed in the deep power-down section of th e functional description. 9. the clock must toggle at least one time during t he t xp period. 10. the clock must toggle at least once during the t xsr time. cke n-1 cke n current state command n action n note l l power down x maintain power down l l self refresh x maintain self refresh l l deep power down x maintain deep power down l h power down nop or deselect exit power down 5,6,9 l h self refresh nop or deselect exit self refresh 5,7,1 0 l h deep power down nop or deselect exit deep power dow n 5,8 h l all banks idle nop or deselect precharge power down entry 5 h l bank(s) active nop or deselect active power down entry 5 h l all banks idle auto refresh self refresh entry h l all banks idle burst terminate enter deep power down h h see the other truth tables
rev 1.2 / july. 2009 15 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series current state bank n truth table (command to bank n ) note: 1. the table applies when both cke n -1 and cke n are high, and after t xsr or t xp has been met if the previous state was self refresh or power down. 2. deselect and nop are functionally interchangeabl e. 3. all states and sequences not shown are illegal o r reserved. 4. this command may or may not be bank specific. if a ll banks are being precharged, they must be in a va lid state for precharging. 5. a command other than nop should not be issued to the same bank while a read or write burst with aut o precharge is enabled. 6. the new read or write command could be auto prec harge enabled or auto precharge disabled. current state command action notes cs ras cas we description any h x x x deselect (nop) continue previous operation l h h h nop continue previous operation idle l l h h active select and activate row l l l h auto refresh auto refresh 10 l l l l mode register set mode register set 10 l l h h precharge no action if bank is idle row active l h l h read select column & start read burst l h l l write select column & start write burst l l h l precharge deactivate row in bank (or banks) 4 read (without auto recharge) l h l h read truncate read & start new read burst 5,6 l h l l write truncate read & start new write burst 5,6,13 l l h l precharge truncate read, start precharge l h h l burst terminate burst terminate 11 write (without auto precharge) l h l h read truncate write & start new read burst 5,6,12 l h l l write truncate write & start new write burst 5,6 l l h l precharge truncate write, start precharge 12
rev 1.2 / july. 2009 16 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series 7. current state definitions: idle: the bank has been precharged, and trp has been met. row active: a row in the bank has been activated , and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with au to precharge disabled, and has not yet terminated o r been terminated. 8. the following states must not be interrupted by a command issued to the same bank. deselect or nop commands or allowable commands to the other bank should be issued on any clock edg e occurring during these states. allowable commands to the other bank are determined by its current state and truth table3, and according to truth table 4. precharging: starts with the registration of a precharge command and ends when t rp is met. once t rp is met, the bank will be in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the '' row active '' state. read with ap enabled: starts with the registrat ion of the read command with auto precharge enabled and ends when t rp has been met. once t rp has been met, the bank will be in the idle state. write with ap enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. 9. the following states must not be interrupted by any executable command; deselect or nop commands mu st be applied to each positive clock edge during these states . refreshing: starts with registration of an auto r efresh command and ends when t rfc is met. once t rfc is met, the lp ddr will be in an '' all banks idle '' state. accessing mode register: starts with registrati on of a mode register set command and ends when tmrd has been met. once t mrd is met, the lp ddr will be in an '' all banks idle '' state. precharging all: starts with the registration o f a precharge all command and ends when t rp is met. once t rp is met, the bank will be in the idle state. 10. not bank-specific; requires that all banks are i dle and no bursts are in progress. 11. not bank-specific. burst terminate affects the mo st recent read burst, regardless of bank. 12. requires appropriate dm masking. 13. a write command may be applied after the comple tion of the read burst; otherwise, a burst terminate must be used to end the read prior to asserting a write command.
rev 1.2 / july. 2009 17 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series current state bank n truth table (command to bank m ) current state command action notes cs ras cas we description any h x x x deselect (nop) continue previous operation l h h h nop continue previous operation idle x x x x any any command allowed to bank m row activating, active, or pre- charging l l h h active activate row l h l h read start read burst 8 l h l l write start write burst 8 l l h l precharge precharge read with auto precharge dis- abled l l h h active activate row l h l h read start read burst 8 l h l l write start write burst 8,10 l l h l precharge precharge write with auto precharge dis- abled l l h h active activate row l h l h read start read burst 8,9 l h l l write start write burst 8 l l h l precharge precharge read with auto precharge l l h h active activate row l h l h read start read burst 5,8 l h l l write start write burst 5,8,10 l l h l precharge precharge write with auto precharge l l h h active activate row l h l h read start read burst 5,8 l h l l write start write burst 5,8 l l h l precharge precharge
rev 1.2 / july. 2009 18 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series note: 1. the table applies when both cke n -1 and cke n are high, and after t xsr or t xp has been met if the previous state was self refresh or power down. 2. deselect and nop are functionally interchangeabl e. 3. all states and sequences not shown are illegal o r reserved. 4. current state definitions: idle: the bank has been precharged, and trp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet termi nated or been terminated. write: a write burst has been initiated , with auto precharge disabled, and has not yet ter minated or been terminated. 5. read with ap enabled and write with ap enabled: the read with autoprecharge enabled or write with a utoprecharge enabled states can be broken into two p arts: the access period and the precharge period. f or read with ap, the precharge period is defined as if the sam e burst was executed with auto precharge disabled a nd then followed with the earliest possible precharge command tha t still accesses all the data in the burst. for wri te with auto precharge, the precharge period begins when t wr ends, with t wr measured as if auto precharge was disabled. the acc ess period starts with registration of the command and end s where the precharge period (or t rp ) begins. during the precharge period, of the read with autoprecharge enabled o r write with autoprecharge enabled states, active, precharge, read, and write commands to the other bank may be applied; during the access period, only active and precharge commands to the other banks may be applied. in e ither case, all other related limitations apply (e. g. contention between read data and write data must be avoided). 6. auto refresh, self refresh, and mode register se t commands may only be issued when all bank are idl e. 7. a burst terminate command cannot be issued to an other bank; it applies to the bank represented by t he current state only. 8. reads or writes listed in the command column inc lude reads and writes with auto precharge enabled a nd reads and writes with auto precharge di sabled. 9. requires appropriate dm masking. 10. a write command may be applied after the comple tion of data output, otherwise a burst terminate com mand must be issued to end the read prior to asserting a write command.
rev 1.2 / july. 2009 19 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series absolute maximum rating ac and dc operating conditions operating condition clock inputs (ck, ck ) address and command inputs (a0~an, ba0, ba1, cke, cs , ras , cas , we ) data inputs (dq, dm, dqs) data outputs (dq, dqs) parameter symbol rating unit operating case temperature t c -30 ~ 85 o c storage temperature t stg -55 ~ 150 o c voltage on any pin relative to v ss v in , v out -0.3 ~ v ddq +0.3 v voltage on v dd relative to v ss v dd -0.3 ~ 2.7 v voltage on v ddq relative to v ss v ddq -0.3 ~ 2.7 v short circuit output current i os 50 ma power dissipation p d 0.7 w parameter symbol min typ max unit note supply voltage v dd 1.7 1.8 1.95 v 1 i/o supply voltage v ddq 1.7 1.8 1.95 v 1 operating case temperature t c -30 85 o c parameter symbol min max unit note dc input voltage v in -0.3 v ddq+ 0.3 v dc input differential voltage v id(dc) 0.4*v ddq v ddq+ 0.6 v 2 ac input differential voltage v id(ac) 0.6*v ddq v ddq+ 0.6 v 2 ac differential crosspoint voltage v ix 0.4*v ddq 0.6*v ddq v 3 parameter symbol min max unit note input high voltage v ih 0.8*v ddq v ddq+ 0.3 v input low voltage v il -0.3 0.2*v ddq v parameter symbol min max unit note dc input high voltage v ihd(dc) 0.7*v ddq v ddq+ 0.3 v dc input low voltage v ild(dc) -0.3 0.3*v ddq v ac input high voltage v ihd(ac) 0.8*v ddq v ddq+ 0.3 v ac input low voltage v ild(ac) -0.3 0.2*v ddq v parameter symbol min max unit note dc output high voltage (ioh = -0.1ma) v oh 0.9*v ddq - v dc output low voltage (iol = 0.1ma) v ol - 0.1*v ddq v
rev 1.2 / july. 2009 20 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series leakage current note: 1. all voltages are referenced to vss = 0v and vssq must be same potential and vddq must not exceed th e level of vdd. 2. vid(dc) and vid(ac) are the magnitude of the differ ence between the input level on ck and the input le vel on ck . 3. the value of vix is expected to be 0.5*vddq and must track variations in the dc level of the same. 4. v in = 0 to 1.8v. all other pins are not tested under v in =0v. 5. d out is disabled. v out = 0 to 1.95v. ac operating test condition note: 1. the circuit shown on the right represents the timing load used in defining the relevant timing parameters of the part. it is not intended to be either a precise repre- sentation of the typical system environment nor a de pic- tion of the actual load presented by a production te ster. system designers will use ibis or other simulation tools to correlate the timing reference load to system env iron- ment. manufacturers will correlate to their producti on (generally a coaxial transmission line terminated a t the tester electronics). for the half strength driver wi th a nominal 10pf load parameters tac and tqh are expected to be in the same range. however, these parameters are not subject to production test but a re estimated by design and characterization. use of ibi s or other simulation tools for system design valida tion is suggested. input / output capacitance note: 1. these values are guaranteed by design and are te sted on a sample base only. 2. these capacitance values are for single monolithi c devices only. multiple die packages will have par allel capacitive loads. 3. input capacitance is measured according to jep14 7 procedure for measuring capacitance using a vector network analyzer. vdd, vddq are applied and all other pins (except the pin under test) floating. dq ' s should be in high impedance state. this may be achieved by pulling cke to low level. 4. although dm is an input-only pin, the input capa citance of this pin must model the input capacitanc e of the dq and dqs pins. this is required to match signal propagation times of dq, dqs and dm in the system. parameter symbol min max unit note input leakage current i li -1 1 ua 4 output leakage current i lo -1.5 1.5 ua 5 parameter symbol value unit note ac input high/low level voltage v ih / v il 0.8*v ddq /0.2*v ddq v input timing measurement reference level voltage v trip 0.5*v ddq v input rise/fall time t r / t f 1 ns output timing measurement reference level voltage v outref 0.5*v ddq v output load capacitance for access time measurement cl pf 1 parameter symbol speed unit note min max input capacitance, ck, ck cck 1.5 3.5 pf input capacitance delta, ck, ck cdck - 0.25 pf input capacitance, all other input-only pins ci 1.5 3 .0 pf input capacitance delta, all other input-only pins cdi - 0.5 pf input/output capacitance, dq, dm, dqs cio 2.0 4.5 pf 4 input/output capacitance delta, dq, dm, dqs cdio - 0. 5 pf 4 test load for full drive strength buffer (20 pf) test load for half drive strength buffer (10 pf) output output output output z o =50r
rev 1.2 / july. 2009 21 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series mobile ddr output slew rate characterristics note: 1. measured with a test load of 20pf connected to vs sq 2. output slew rate for rising edge is measured betw een vild(dc) to vihd(ac) and for falling edge betwee n vihd(dc) to vild(ac) 3. the ratio of pull-up slew rate to pull-down slew rate is specified for the same temperature and voltag e, over the entire temperature and voltage range. for a given output, it represent s the maximum difference between pull-up and pull-dow n drivers due to process variation. mobile ddr ac overshoot / undershoot specification note: 1. this specification is intended for devices with no clamp protection and is guaranteed by design. parameter min max unit note pull-up and pull-down slew rate for full strength d river 0.7 2.5 v/ns 1, 2 pull-up and pull-down slew rate for half strength d river 0.3 1.0 v/ns 1, 2 output slew rate matching ratio (pull-up to pull-do wn) 0.7 1.4 - 3 parameter specification maximum peak amplitude allowed for overshoot 0.5v maximum peak amplitude allowed for undershoot 0.5v the area between overshoot signal and vdd must be l ess than or equal to 3v-ns the area between undershoot signal and gnd must be less than or equal to 3v-ns 2.5v 2.0v 1.5v 1.0v 0.5v 0.0v -0.5v overshoot undershoot vdd vss max. amplitude = 0.5v max. area = 3v-ns time (ns) voltage (v)
rev 1.2 / july. 2009 22 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series dc characteristics parameter symbol test condition max unit note ddr 400 ddr 370 ddr 333 ddr 266 drr 200 operating one bank active-precharge current idd0 trc = trc(min); tck = tck(min); cke is high; cs is high between valid commands; address inputs are switching; data bus inputs are stable 45 40 35 35 35 ma 1 precharge power-down standby current idd2p all banks idle; cke is low; cs is high; tck = tck(min); address and control inputs are switching; data bus inputs are stable 0.3 ma precharge power-down standby current with clock stop idd2ps all banks idle; cke is low; cs is high; ck = low; ck = high; address and control inputs are switching; data bus inputs are stable 0.3 ma precharge non power-down standby current idd2n all banks idle; cke is high; cs is high, tck = tck(min); address and control inputs are switching; data bus inputs are stable 12 ma precharge non power-down standby current with clock stop idd2ns all banks idle; cke is high; cs is high; ck = low; ck = high; address and control inputs are switching; data bus inputs are stable 8 active power-down standby current idd3p one bank active; cke is low; cs is high; tck = tck(min); address and control inputs are switching; data bus inputs are stable 5 ma active power-down standby current with clock stop idd3ps one bank active; cke is low; cs is high; ck = low; ck = high; address and control inputs are switching; data bus inputs are stable 3 active non power-down standby current idd3n one bank active; cke is high; cs is high; tck = tck (min); address and control inputs are switching; data bus inputs are stable 15 ma active non power-down standby current with clock stop idd3ns one bank active; cke is high; cs is high; ck = low; ck = high; address and control inputs are switching; data bus inputs are stable 10 ma operating burst read cur- rent idd4r one bank active; bl=4; cl=3; tck = tck (min) ; continuous read bursts; iout=0ma; address in- puts are switching, 50% data change each burst transfer 100 95 90 80 80 ma 1 operating burst write cur- rent idd4w one bank active; bl=4; tck=tck (min) ; continu- ous write bursts; address inputs are switching; 50% data change each burst transfer 100 95 90 80 80 ma auto refresh current idd5 trc=trfc (min) ; tck=tck (min); burst refresh; cke is high; address and control inputs are switching; data bus inputs are stable 70 ma self refresh current idd6 cke is low; ck=low; ck =high; extended mode register set to all 0's; address and control inputs are stable; data bus inputs are stable see next page ua 2 deep power down current idd8 address, control and dat a bus inputs are stable 10 ua 4
rev 1.2 / july. 2009 23 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series note: 1. idd specifications are tested after the device is properly initialized 2. input slew rate is 1v/ns 3. definitions for idd: low is defined as v in 0.1 * v ddq high is defined as v in 0.9 * v ddq stable is defined as inputs stable at a high or low level switching is defined as - address and command: inputs changi ng between high and low once per two clock cycles - data bus inputs: dq changing betwe en high and low once per clock cycle dm and dqs are stable 4. please contact hynix office for more information a nd ability for dpd operation. deep power down operat ion is a hynix optional function. 5. all idd values are guaranteed by full range of op erating voltage and temperature. vdd, vddq = 1.7v ~ 1.95v. temperature = -30 o c ~ +85 o c dc characteristics - i dd6 note: 1. related numerical values in this 45 o c are examples for reference sample value only. 2. with a on-chip temperature sensor, auto temperat ure compensated self refresh will automatically adjus t the interval of self-refresh operation according to case temperature variations. temp. ( o c) memory array unit 4 banks 2 banks 1 bank 45 200 150 130 ua 85 320 280 250 ua
rev 1.2 / july. 2009 24 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series ac characteristics (ac operating conditions unless otherwise noted) (s heet 1 of 2) parameter symbol ddr400 ddr370 ddr333 ddr266 ddr200 unit note min max min max min max min max min max dq output access time (from ck, ck ) t ac 2.0 5.0 2.0 5.0 2.0 5.0 2.5 6.0 2.5 7.0 ns dqs output access time (from ck, ck ) t dqsck 2.0 5.0 2.0 5.0 2.0 5.0 2.5 6.0 2.5 7.0 ns clock high-level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck clock low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck clock half period t hp tcl, tch (min) - tcl, tch (min) - tcl, tch (min) - tcl, tch (min) - tcl, tch (min) - ns 1,2 system clock cycle time cl = 3 t ck3 5.0 - 5.4 - 6.0 - 7.5 - 10 - ns 3 cl = 2 t ck2 12 - 12 12 12 - 15 - ns dq and dm input setup time t ds 0.48 - 0.54 0.6 0.8 1.1 ns 4,5,6 dq and dm input hold time t dh 0.48 - 0.54 0.6 0.8 1.1 ns 4,5,6 dq and dm input pulse width t dipw 1.4 - 1.6 - 1.6 - 1.6 - 2.2 - ns 7 address and control input setup time t is 0.9 - 1.0 1.1 1.3 1.5 ns 6,8,9 address and control input hold time t ih 0.9 - 1.0 1.1 1.3 1.5 ns 6,8,9 address and control input pulse width t ipw 2.2 - 2.2 - 2.2 - 2.6 - 3.0 - ns 7 dq & dqs low-impedance time from ck, ck t lz 1 - 1.0 - 1.0 - 1.0 - 1.0 - ns 10 dq & dqs high-impedance time from ck, ck t hz - 5.0 5.0 5.0 6.0 7.0 ns 10 dqs - dq skew t dqsq - 0.4 0.45 0.5 0.6 0.7 ns 11 dq / dqs output hold time from dqs t qh thp - tqhs - thp - tqhs thp - tqhs thp - tqhs thp - tqhs ns 2 data hold skew factor t qhs - 0.5 0.5 0.65 0.75 1.0 ns 2 write command to 1st dqs latching transition t dqss 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tck dqs input high-level width t dqsh 0.4 - 0.4 0.4 0.4 0.4 tck dqs input low-level width t dqsl 0.4 - 0.4 0.4 0.4 0.4 tck dqs falling edge of ck setup time t dss 0.2 - 0.2 0.2 0.2 0.2 tck dqs falling edge hold time from ck t dsh 0.2 - 0.2 0.2 0.2 0.2 tck
rev 1.2 / july. 2009 25 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series ac characteristics (ac operating conditions unless otherwise noted) (s heet 2 of 2) parameter symbol ddr400 ddr370 ddr333 ddr266 ddr200 unit note min max min max min max min max min max mode register set command period t mrd 2 - 2 - 2 - 2 - 2 - tck mrs(srr) to read command period t srr 2 - 2 - 2 - 2 - 2 - tck minimum time between status register read to next valid command t src cl+1 - cl+1 - cl+1 - cl+1 - cl+1 - tck write preamble setup time t wpres 0 - 0 - 0 - 0 - 0 - ns 12 write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck 13 write preamble t wpre 0.25 - 0.25 - 0.25 - 0.25 - 0.25 - tck read preamble cl = 3 t rpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tck 14 cl = 2 t rpre 0.5 1.1 0.5 1.1 0.5 1.1 0.5 1.1 0.5 1.1 tck 14 read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck active to precharge command period t ras 40 70,00 0 42 70,00 0 42 70,00 0 45 70,00 0 50 70,00 0 ns active to active command period t rc 55 - 58.2 - 60 - 75 - 80 - ns auto refresh to active/auto refresh command period t rfc 72 - 72 - 72 - 72 - 72 - ns active to read or write delay t rcd 15 - 16.2 - 18 - 22.5 - 30 - ns 15 precharge command period t rp 15 - 16.2 - 18 - 22.5 - 30 - ns 15 active bank a to active bank b delay t rrd 10 - 10.8 - 12 - 15 - 15 - ns write recovery time t wr 15 - 15 - 15 - 15 - 15 - ns auto precharge write recovery + precharge time t dal (twr/tck) + (trp/tck) tck 16 internal write to read command delay t wtr 1 - 1 - 1 - 1 - 1 - tck self refresh exit to next valid command delay t xsr 120 - 120 - 120 - 120 - 120 - ns exit power down to next valid command delay t xp tis + 2clk - tis + 1clk - tis + 1clk - tis + 1clk - tis + 1clk - ns cke min . pulse width (high and low) t cke 1 - 1 - 1 - 1 - 1 - tck average periodic refresh interval t refi - 7.8 - 7.8 - 7.8 - 7.8 - 7.8 us 17 refresh period t ref - 64 - 64 - 64 - 64 - 64 ms
rev 1.2 / july. 2009 26 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series note: 1. min (t cl , t ch ) refers to the smaller of the actual clock low time and the actual clock high time as provided to the d evice (i.e. this value can be greater than the minimum specification limits for t cl and t ch ) 2. t qh = t hp - t qhs , where thp = minimum half clock period for any giv en cycle and is defined by clock high or clock low ( t cl , t ch ). t qhs accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of dqs on one transition followed by the worst case pull-in of dq on the next transition, bot h of which are, separately, due to data pin skew an d output pattern effects, and p-channel to n-channel variation of the output drive rs. 3. the only time that the clock frequency is allowed to change is during clock stop, power-down or self- refresh modes. 4. the transition time for dq, dm and dqs inputs is measured between v il (dc) to v ih (ac) for rising input signals, and v ih (dc) to v il (ac) for falling input signals. 5. dqs, dm and dq input slew rate is specified to pr event double clocking of data and preserve setup and hold times. signal transitions through the dc region must be monotonic. 6. input slew rate 1.0 v/ns. 7. these parameters guarantee device timing but the y are not necessarily tested on each device. 8. the transition time for address and command input s is measured between v ih and v il . 9. a ck/ck differential slew rate of 2.0 v/ns is assumed for t his parameter. 10. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device i s no longer driving (hz), or begins driving (lz). 11. t dqsq consists of data pin skew and output pattern effects , and p-channel to n-channel variation of the output drivers for any given cycle. 12. the specific requirement is that dqs be valid (h igh, low, or some point on a valid transition) on o r before this ck edge. a valid transition is defined as monotonic and meeting the i nput slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in progre ss, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . 13. the maximum limit for this parameter is not a d evice limit. the device operates with a greater val ue for this parameter, but system performance (bus turnaround) will degrade accordingl y. 14. a low level on dqs may be maintained during hig h-z states (dqs drivers disabled) by adding a weak pull-down element in the system. it is recommended to turn off the weak pull- down element during read and write bursts (dqs driv ers enabled). 15. speed bin (cl-t rcd -t rp ) = 3-3-3 16. t dal = (t wr /t ck ) + (t rp /t ck ): for each of the terms above, if not already an int eger, round to the next higher integer. 17. a maximum of eight refresh commands can be posted to any given low power ddr sdram (mobile ddr sdram ), meaning that the maximum absolute interval between any refresh co mmand and the next refresh command is 8*t refi . 18. all ac parameters are guaranteed by full range o f operating voltage and temperature. vdd, vddq = 1.7v ~ 1.95v. temperature = -30 o c ~ +85 o c.
rev 1.2 / july. 2009 27 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series mobile ddr sdram operation state diagram idle all bank pcg. auto refresh self refresh pcg. power down (e)mrs set write read precharge all active power down row active mrs, emrs refs ckel refa ckeh act ckel ckeh write write read refsx command input automatic sequence deep power down power on pcg. all banks power applied dpds dpdsx burst stop writea read reada bst read a write a writea reada read pre pre pre srr read srr read reada act : active b st : b urst ckel : e nter pow er-dow n ckeh : e xit pow er-dow n dpds : e nter deep pow er-dow n dpdsx : e xit deep pow er- dow nem r s e m rs : e xt. m ode reg. set m r s : m ode register set pr e : precharge pr eall : precharge all b anks r efa : auto r efresh r efs : e nter self r efresh r efsx : e xit self refresh r ead : r ead w /o auto precharge r ead a : r ead w ith auto precharge w r ite : w rite w /o auto precharge w r itea : w rite w ith auto precharge sr r : status r egister r ead
rev 1.2 / july. 2009 28 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series deselect the deselect function (cs = high) prevents new commands from being executed by the mobile ddr sdram. the mobile ddr sdram is effectively deselected. operati ons already in progress are not affected. no operation the no operation (nop) command is used to perform a nop to a mobile ddr sdram that is selected (cs = low). this prevents unwanted commands from being register ed during idle or wait states. operations already i n progress are not affected. (see to next figure) active the active command is used to activate a row in a p articular bank for a subsequent read or write acces s. the value of the ba0,ba1 inputs selects the bank, and the addres s provided on a0-a12 (or the highest address bit) s elects the row. (see to next figure) before any read or write commands can be issued to a bank within the mobile ddr sdram, a row in that b ank must be opened. this is accomplished via the active command, which selects both the bank and the row t o be acti- vated. the row remains active until a precharge (or read w ith auto precharge or write with auto precharge) co m- mand is issued to the bank. a precharge (or read with auto precharge or write w ith auto precharge) command must be issued before opening a different row in the same bank. cs a0~a12 we cas don't care clk clk cke ba0, ba1 bank address row address don't care ra ba nop command active command ras cs a0~a12 w e cas clk clk cke ba0, ba1 ras (high) (high)
rev 1.2 / july. 2009 29 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series once a row is open (with an active command) a read or write command may be issued to that row, subject to the t rcd specification. t rcd ( min ) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be ent ered. a subsequent active command to a different row in t he same bank can only be issued after the previous active row has been closed (precharge). the minimum time inter val between successive active commands to the same bank is defined by t rc . a subsequent active command to another bank can be issued while the first bank is being accessed, whic h results in a reduction of total row-access overhead. the minim um time interval between successive active commands to differ- ent banks is defined by t rrd. d on't c are once a row is open(w ith an active com m and) a read o r w rite com m and m ay be issued to that row , subject to the trcd specification. trcd (m in) should be divided by the clock period and rounded up to the next w hole num ber to determ ine the earliest clock edge after the active com m and on which a read or w rite com m and can be ent ered . /clk clk n op nop nop nop trcd com m and address w rite a w ith a/p bank b act nop bank a act bank a col bank b row bank a row bank a act bank a row trrd trc
rev 1.2 / july. 2009 30 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series read / write command the read command is used to initiate a burst read t o an active row. the value of ba0 and ba1 selects t he bank and address inputs select the starting column location. the value of a10 determines whether or not auto pre charge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row w ill remain open for subsequent access. the valid data-out elements will be available cas latency after the read comman d is issued. the mobile ddr drives the dqs during read operation s. the initial low state of the dqs is known as the read preamble and the last data-out element is coincident with th e read postamble. dqs is edge-aligned with read dat a. upon com- pletion of a burst, assuming no new read commands h ave been initiated, the i/o's will go high-z. the write command is used to initiate a burst write access to an active row. the value of ba0, ba1 sel ects the bank and address inputs select the starting column locat ion. the value of a10 determines whether or not auto pre charge is used.if auto precharge is selected, the r ow being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent access. input data appearing on the data bus, is written to the memory array subject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the correspond ing data will be written to the memory; if the dm signal is register ed high, the corresponding data-inputs will be igno red, and a write will not be executed to that byte/column location. the memory controller drives the dqs during write o perations. the initial low state of the dqs is known as the write preamble and the low state following the last data- in element is write postamble. upon completion of a burst, assuming no new commands have been initiated, the i/o's will st ay high-z and any additional input data will be ignored. read / write command don't care ca ba high to enable auto precharge low to disable auto precharge read com m and w rite com m and ca ba clk clk cke clk clk cke (high) (high) cs a0~a8 w e cas a10 ras ba0, ba1 cs a0~a8 w e cas a10 ras ba0, ba1
rev 1.2 / july. 2009 31 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series read the basic read timing parameters for dq are shown n ext figure (basic read timing parameters). they app ly to all read operations. during read bursts, dqs is driven by the mobile ddr sdram along with the output data. the initial low state of the dqs is known as the read preamble; the low state coincident with last data-out elemen t is known as the read postamble. basic read timing parameters d o n d o n+ 1 d o n+ 2 d o n+ 3 /c lk clk tck tck tc h tc l tr pre td q sc k td q sq m ax ta c tlz tq h td q sc k tq h tq h th z tq h tr pr e td q sc k tlz td q sc k trpst ta c td q s q m ax d o n d o n+ 1 d o n+ 2 d o n + 3 d q s d q d q s d q d o n 't c a re 1) d o n : d a ta o ut from co lu m n n 2) all d q are vaild ta c after th e c k edge all d q are vaild td q sq after th e d q s edge, rega rdless of ta c trpst ta c m a x ta c m in tq h th z
rev 1.2 / july. 2009 32 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series the first data-out element is edge aligned with the first rising edge of dqs and the successive data-o ut elements are edge aligned to successive edges of dqs. this is sh own in next figure with a cas latency of 2 and 3. upon completion of a read burst, assuming no other read command has been initiated, the dq will go to high-z. r ead burst showing cas latency /clk clk do n do n read nop nop nop nop nop ba, col n cl =3 cl =2 don't care 1) do n : data out from column n 2) ba, col n = bank a, column n 3) burst length = 4; 3 subseqnent elements of data out appear in the programmed order following do n 4) shown with nominal tac, tdqsck and tdqsq command address dqs dq dqs dq
rev 1.2 / july. 2009 33 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series read to read data from a read burst may be concatenated or trunc ated by a subsequent read command. the first data f rom the new burst follows either the last element of a comp leted burst or the last desired element of a longer burst that is being truncated. the new read command should be iss ued x cycles after the first read command, where x equals the number of desired data-out element pairs (pairs are required by the 2n prefetch architecture). consecutive read bursts a read command can be initiated on any clock cycle following a previous read command. non-consecutive reads are shown in the first figure of next page. random read accesses within a page or pages can be performed a s shown in second figure of next page. /c lk c lk d o n d o n rea d n o p r ea d n o p n o p n o p ba , c ol n c l = 3 c l = 2 d on't c are 1) d o n (or b ): d ata out from colum n n (or colum n b) 2) ba , c ol n (b) = bank a , c olum n n (b) 3) burst length = 4 or 8 (if 4 , the bursts are conc atenated; if 8, the second burst interrupts the fir st) 4) r ead bursts are to an active row in any bank 5) show n w ith nom inal ta c, td q sc k and td q sq co m m an d a ddress d q s d q d q s d q ba , c ol b d o b d o b
rev 1.2 / july. 2009 34 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series non-consecutive read bursts random read bursts / c l k c l k d o n d o n r e a d n o p n o p r e a d n o p n o p b a , c o l n c l = 3 c l = 2 d o n 't c a r e 1 ) d o n ( o r b ) : d a t a o u t fr o m c o lu m n n ( o r c o lu m n b ) 2 ) b a , c o l n ( b ) = b a n k a , c o lu m n n ( b ) 3 ) b u r s t l e n g t h = 4 ; 3 s u b s e q u e n t e le m e n t s o f d a t a o u t a p p e a r in th e p r o g r a m m e d o r d e r fo llo w in g d o n ( b ) 4 ) s h o w n w it h n o m in a l t a c , t d q s c k a n d t d q s q c o m m a n d a d d r e s s d q s d q d q s d q b a , c o l b d o b / c l k c l k d o n d o x ' d o n r e a d r e a d r e a d r e a d n o p n o p b a , c o l n c l = 3 c l = 2 d o n 't c a r e 1 ) d o n , e t c : d a t a o u t f r o m c o lu m n n , e t c n ', x ', e t c : d a t a o u t e le m e n t s , a c c o d in g t o t h e p r o g r a m m d b u r s t o r d e r 2 ) b a , c o l n = b a n k a , c o lu m n n 3 ) b u r s t l e n g t h = 2 , 4 o r 8 in c a s e s s h o w n ( i f b u r s t o f 4 o r 8 , t h e b u r s t is in t e r r u p t e d ) 4 ) r e a d a r e t o a c t i v e r o w s in a n y b a n k s c o m m a n d a d d r e s s d q s d q d q s d q b a , c o l b d o b b a , c o l x b a , c o l g d o n ' d o x d o x ' d o b ' d o g d o g ' d o n ' d o x d o b d o b '
rev 1.2 / july. 2009 35 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series read burst terminate data from any read burst may be truncated with a bu rst terminate command. the burst terminate latency is equal to the read (cas) latency, i.e., the burst te rminate command should be issued x cycles after the read com- mand where x equals the desired data-out element pa irs. terminating a read burst /clk clk r ead bu rst term inate n o p n o p n o p n o p ba, col n cl = 3 cl = 2 d on't care 1) d o n : d ata out from colum n n 2) ba, col n = bank a, colum n n 3) cases show n are bursts of 4 or 8 term inated afte r 2 data elem ents 4) show n w ith nom inal tac, td q sck and td q sq com m and address d q s dq d q s dq
rev 1.2 / july. 2009 36 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series read to write data from read burst must be completed or truncated before a subsequent write command can be issued. i f trun- cation is necessary, the burst terminate command mu st be used, as shown in next fig. for the case of n ominal t dqss . read to write /clk clk d o n d o n read bst n o p w r ite n o p ba, col n cl = 3 cl = 2 don't care 1) d o n = d ata o ut from colum n n; d i b = d ata in to colum n b 2) burst length = 4 or 8 in the cases show n; if the burst length is 2, the bst com m and can be om m itted 3) show n w ith nom inal tac, td q sck and td qsq com m and address d q s d q d q s d q ba, col b n o p dm read bst n o p n o p n o p ba, col n com m and address ba, col b w rite td qss d i b di b
rev 1.2 / july. 2009 37 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series read to precharge a read burst may be followed by or truncated with a precharge command to the same bank (provided auto pre- charge was not activated). the precharge command sh ould be issued x cycles after the read command, whe re x equal the number of desired data-out element pairs. following the precharge command, a subsequent comma nd to the same bank cannot be issued until trp is m et. note that part of the row precharge time is hidden during the access of the last data-out elements.in the case of a read being executed to completion, a precharge comm and issued at the optimum time (as described above) pro- vides the same operation that would result from rea d burst with auto precharge enabled. the disadvantage of the precharge command is that i t requires that the command and address buses be av ailable at the appropriate time to issue the command. the adva ntage of the precharge command is that it can be us ed to truncate bursts. read to precharge /clk clk do n do n read nop pre nop nop act ba, col n cl =3 cl =2 don't care 1) do n = data out from column n 2) cases shown are either uninterrupted burst of 4, or interrupted bursts of 8 3) shown with nominal tac, tdqsck and tdqsq 4) precharge may be applied at (bl / 2) tck after t he read command. 5) note that precharge may not be issued before tra s ns after the active command for applicable banks. 6) the active command may be applied if trc has bee n met. command address dqs dq dqs dq bank ( a or all) ba, row trp
rev 1.2 / july. 2009 38 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series write input data appearing on the data bus, is written to the memory array subject to the dm input logic lev el appearing coincident with the data. if a given dm signal is r egistered low, the corresponding data will be writt en to the memory; if the dm signal is registered high, the correspond ing data inputs will be ignored, and a write will n ot be executed to that byte / column location. basic write timing parameters for dq are shown in f igure; they apply to all write operations. basic write timing parameters during write bursts, the first valid data-in elemen t will be registered on the first rising edge of dq s following the write command, and the subsequent data elements wil l be registered on successive edges of dqs. the low state of dqs between the write command and the first rising edge is called the write preamble, and the low stat e on dqs following the last data-in element is called the wr ite postamble. the time between the write command and the first co rresponding rising edge of dqs (t dqss ) is specified with a rel- atively wide range - from 75 % to 125 % of a clock cycle. next fig. shows the two extremes of t dqss for a burst of 4. upon completion of a burst, assuming no other comma nds have been initiated, the dq will remain high-z and any additional input data will be ignored. /c lk c lk tc k tc h tc l d i n d i n d q s d q s d q , d m d q , d m td q ss td q sh td sh td sh tw pst tw pr es td s td h tw pre td s td h tw pr es tw pre td q ss td q sh tw pst td ss td ss td q sl d o n 't c a re 1) d i n: d ata in for colum n n 2) 3 subseq uent elem ents of d ata in are ap p lied in the p rog ram m ed ord er follow ing d i n 3) td q ss : each rising edg e of d q s m ust fall w ithin the + /-25 (p ercentage) w ind ow of the corresp onding positive clock edg e td q sl case 1: td q ss = m in case 2: td q ss = m ax
rev 1.2 / july. 2009 39 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series write burst (min. and max. t dqss ) /clk clk w rite nop no p no p nop ba, col b td qss m in don't care 1) di b = data in to colum n b 2) 3 subsequent elem ents of data in are applied in the program m ed order following di b 3) a non-interrupted burst of 4 is shown 4) a10 is low with the w rite com m and (auto precharg e is disabled) com m and address dqs dq dqs dq no p d m d m tdqss m ax
rev 1.2 / july. 2009 40 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series write to write data for any write burst may be concatenated with o r truncated with a subsequent write command. in eit her case, a continuous flow of input data, can be maintained. the new write command can be issued on any positiv e edge of the clock following the previous write command.the first data-in element from the new burst is applied after either the last element of a completed burst or the last d esired data element of a longer burst which is bein g truncated. the new write command should be issued x cycles after t he first write command, where x equals the number o f desired data-in element pairs. concatenated write bursts /clk clk write nop write nop nop ba, col b tdqss min don't care 1) di b ( n ) = data in to column b (column n) 2) 3 subsequent elements of data in are applied in the programmed order following di b. 3 subsequent elements of data in are applied in the programmed order following di n. 3) non-interrupted bursts of 4 are shown. 4) each write command may be to any active bank command address dqs dq dqs dq nop dm dm ba, col n di b di n di b di n tdqss max
rev 1.2 / july. 2009 41 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series non-concatenated write bursts random write cycles /c lk c l k w r it e n o p n o p w r it e n o p b a , c o l b d on 't c a re 1 ) d i b ( n ) = d a ta in to co lu m n b (o r co lu m n n ). 2 ) 3 su b se q u e n t e le m e n ts o f d a ta in a re a p p lie d in th e p ro g ra m m e d o rd e r fo llo w in g d i b . 3 su b se q u e n t e le m e n ts o f d a ta in a re a p p lie d in th e p ro g ra m m e d o rd e r fo llo w in g d i n . 3 ) n o n -in te rru p te d b u rsts o f 4 a re sh o w n . 4 ) e a ch w r it e co m m a n d m a y b e to a n y a ctive b a n k a n d m a y b e to th e sa m e o r d iffe re n t d e v ice s . c om m a n d a d d ress d q s d q n o p d i b d m td q s s m a x d i n b a , c o l n /c lk c lk w r it e w r it e w r it e w r it e n o p b a , c ol b d on't c are 1 ) d i b etc. = d a ta in to colum n b, e tc. ; b', etc. = th e next d ata in fo llo w in g d i b, etc. a cco rding to the program m ed burst order 2 ) pro gram m ed burst length = 2, 4 or 8 in cases sho w n. if burst of 4 or 8, burst w ould be truncate d. 3 ) each w r it e co m m and m ay be to an y active ban k an d m ay be to the sam e o r diffe rent devices. c om m and a d d ress w r it e b a , c ol n b a , c ol x ba , c ol a b a , c ol g d q s d m td q ss m ax d q d i b d i b ' d i x d i x' d i n d i n ' d i a d i a'
rev 1.2 / july. 2009 42 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series write to read data for any write burst may be followed by a subse quent read command. to follow a write without trunc ating the write burst, twtr should be met as shown in figure. data for any write burst may be truncated by a subs equent read command as shown in figure. note that t he only data-in pairs that are registered prior to the t wtr period are written to the internal array, and any subsequent data-in must be masked with dm. /clk clk write nop nop nop nop ba, col b don't care 1) di b = data in to column b . 3 subsequent elements of d ata in are applied in the programmed order followin g di b. 2) a non-interrupted burst of 4 is shown. 3) twtr is referenced from the positive clock edge after the last data in pair. 4) a10 is low with the write command (auto precharg e is disabled) 5) the read and write commands are to the same devi ce but not necessarily to the same bank. command address dqs dq read dm tdqss max ba, col n twtr cl=3 nop di b
rev 1.2 / july. 2009 43 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series interrupting write to read /clk clk write nop nop read nop ba, col b don't care 1) di b = data in to column b. do n = data out from column n. 2) an interrupted burst of 4 is shown, 2 data eleme nts are written. 3 subsequent elements of data in are applied in the programmed order following di b. 3) twtr is referenced from the positive clock edge after the last data in pair. 4) a10 is low with the write command (auto precharg e is disabled) 5) the read and write commands are to the same devi ce but not necessarily to the same bank. command address dqs dq nop dm tdqss max twtr cl=3 nop di b ba, col n do n
rev 1.2 / july. 2009 44 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series write to precharge data for any write burst may be followed by a subse quent precharge command to the same bank (provided auto precharge was not activated). to follow a write wit hout truncating the write burst, twr should be met as shown in fig. non-interrupting write to precharge /clk clk write nop nop nop pre ba, col b don't care 1) di b (n) = data in to column b (column n) 3 subsequent elements of data in are applied in the programmed order following di b. 2) a non-interrupted bursts of 4 are shown. 3) twr is referenced from the positive clock edge a fter the last data in pair. 4) a10 is low with the write command (auto precharg e is disabled) command address dqs dq nop dm tdqss max ba (a or all) twr di b
rev 1.2 / july. 2009 45 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series data for any write burst may be truncated by a subs equent precharge command as shown in figure. note that only data-in pairs that are registered pr ior to the t wr period are written to the internal array, and any subse- quent data-in should be masked with dm, as shown in next fig. following the precharge command, a subse quent command to the same bank cannot be issued until trp is met. interrupting write to precharge /clk clk write nop nop nop nop ba, col b don't care 1) di b = data in to column b . 2) an interrupted burst of 4 or 8 is shown, 2 data elements are written. 3) twr is referenced from the positive clock edge a fter the last desired data in pair. 4) a10 is low with the write command (auto precharg e is disabled) 5) *1 = can be don't care for programmed burst leng th of 4 6) *2 = for programmed burst length of 4, dqs becom es don't care at this point command address dqs dq pre dm tdqss max twr di b * 2 * 1 * 1 * 1 * 1 ba (a or all)
rev 1.2 / july. 2009 46 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series burst terminate the burst terminate command is used to truncate rea d bursts (with auto precharge disabled). the most r ecently registered read command prior to the burst terminat e command will be truncated, as shown in the operat ion sec- tion of this datasheet. note the burst terminate co mmand is not bank specific. this command should not be used to terminate write bursts. burst terminate command don't care cs a0~a12 we cas clk clk cke ba0, ba1 ras (high)
rev 1.2 / july. 2009 47 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series precharge the precharge command is used to deactivate the ope n row in a particular bank or the open row in all b anks. another command to the same bank (or banks) being p recharged must not be issued until the precharge ti me (t rp ) is completed. if one bank is to be precharged, the particular ban k address needs to be specified. if all banks are t o be precharged, a10 should be set high along with the precharge com mand. if a10 is high, ba0 and ba1 are ignored. a pr echarge command will be treated as a nop if there is no ope n row in that bank, or if the previously open row i s already in the process of precharging. precharge command auto precharge auto precharge is a feature which performs the same individual bank precharge function as described ab ove, but with- out requiring an explicit command. this is accomplished by using a10 (a10=high), to en able auto precharge in conjunction with a specific read or write command. this precharges the bank/row after the rea d or write burst is complete. auto precharge is non persistent, so it should be e nabled with a read or write command each time auto precharge is desired. auto precharge ensures that a precharge is initiated at the earliest valid stage within a bur st. the user must not issue another command to the same bank until the precharge time (t rp ) is completed. don't care ba bank address a10 defines the precharge mode when a precharge command, a read command or a write command is issued. if a10 = high when a precharge command is issued, all banks are precharged. if a10 = low when a precharge command is issued, only the bank that is selected by ba1/ba0 is precharged. if a10 = high when read or write command, auto- precharge function is enabled. while a10 = low, auto- precharge function is disabled. cs a0~a9, a11, a12 we cas clk clk cke ba0, ba1 ras a10 (high)
rev 1.2 / july. 2009 48 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series auto refresh and self refresh mobile ddr devices require a refresh of all rows in any rolling 64ms interval. each refresh is generat ed in one of two ways: by an explicit auto refresh command, or by an internally timed event in self refresh mode: - auto refresh. this command is used during normal operation of the mobile ddr. it is non persistent, so must be issue d each time a refresh is required. the refresh addressing is gene rated by the internal refresh controller.the mobile ddr requires auto refresh commands at an average periodic interv al of t refi . to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the ab solute refresh interval is provided. a maximum of eight auto refre sh commands can be posted to any given mobile ddr, and the maximum absolute interval between any auto refresh command and the next auto refresh command is 8*t refi . -self refresh. this state retains data in the mobile ddr, even if the rest of the system is powered down (even withou t external clock- ing). note refresh interval timing while in self re fresh mode is scheduled internally in the mobile dd r and may vary and may not meet trefi time. ''don't care'' except cke, which must remain low. a n internal refresh cycle is scheduled on self refre sh entry. the pro- cedure for exiting self refresh mode requires a ser ies of commands. first clock must be stable before cke going high. nop commands should be issued for the duration of t he refresh exit time (t xsr ), because time is required for the com- pletion of any internal refresh in progress. the use of self refresh mode introduces the possibi lity that an internally timed event can be missed w hen cke is raised for exit from self refresh mode. upon exit f rom self refresh an extra auto refresh command is r ecom- mended. in the self refresh mode, two additional po wer-saving options exist. they are temperature comp ensated self refresh and partial array self refresh and are desc ribed in the extended mode register section. the self refresh command is used to retain cell dat a in the mobile sdram. in the self refresh mode, th e mobile sdram operates refresh cycle asynchronously. the self refresh command is initiated like an auto refresh command except cke is disabled (low). the m obile ddr can accomplish an special self refresh operation by the specific modes (pasr) programmed in extended m ode regis- ters. the mobile ddr can control the refresh rate a utomatically by the temperature value of auto tcsr (temperature compensated self refresh) to reduce self refresh cu rrent and select the memory array to be refreshed b y the value of pasr (partial array self refresh). the mobile ddr c an reduce the self refresh current(i dd6 ) by using these two modes.
rev 1.2 / july. 2009 49 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series don't care auto refresh command self refresh command cs a0~a12 we cas clk clk cke ba0, ba1 ras cs a0~a12 we cas clk clk cke ba0, ba1 ras (high)
rev 1.2 / july. 2009 50 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series self refresh entry and exit /clk clk enter self refresh mode pre nop arf nop nop nop arf nop act pre all cke command address a10(ap) dq ba a row n row n high-z exit self refresh mode any command (auto refresh recommended) cont't care trp trfc txsr trfc
rev 1.2 / july. 2009 51 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series mode register set the mode register and the extended mode register ar e loaded via the address bits. ba0 and ba1 are used to select among the mode register, the extended mode register and status register. see the mode register descrip tion in the register definition section. the mode register set command can only be issued when all banks are idle and no bursts are in progress, and a subsequent executable command cannot be issued until t mrd is met. mode register set command code = mode register / extended mode register selec tion (ba0, ba1) and op-code (a0 - an) tmrd definition mrs nop valid code valid tmrd /clk clk command address don't care d o n 't c a re c ode c ode c s a 0 ~ a 12 w e c a s c l k c l k c k e b a 0 , b a 1 r a s (h igh )
rev 1.2 / july. 2009 52 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series mode register the mode register contains the specific mode of ope ration of the mobile ddr sdram. this register inclu des the selec- tion of a burst length(2, 4 or 8), a cas latency(2 or 3), a burst type. the mode register set must be done before any activate command after the power up sequence. any c ontents of the mode register be altered by re-progr amming the mode register through the execution of mode registe r set command. mode register set burst length read and write accesses to the mobile ddr sdram are burst oriented, with the burst length being progra mmable, as shown in page10. the burst length determines the ma ximum number of column locations that can be access ed for a given read or write command. burst lengths of 2, 4 or 8 locations are available for both the sequentia l and the interleaved burst types. burst type accesses within a given burst may be programmed to be either sequential or interleaved. cas latency the cas latency is the delay between the registrati on of a read command and the availability of the fi rst piece of out- put data. if a read command is registered at a cloc k edge n and the latency is 3 clocks, the first data elemen t will be valid at n + 2t ck + t ac . if a read command is registered at a clock edge n and the latency is 2 clocks, the first data element will be valid at n + t ck + t ac . clk clk precharge all bank mode register set cm d tck comm and (any) 0 1 2 3 4 5 6 trp 2 clk m in
rev 1.2 / july. 2009 53 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series extended mode register the extended mode register contains the specific fe atures of self refresh operation of the mobile ddr sdram. the extended mode register is programmed via the mo de register set command (with ba1=1 and ba0=0) and will retain the stored information until it is repr ogrammed, the device is put in deep power-down mode , or the device loses power. the extended mode register should be l oaded when all banks are idle and no bursts are in progress, and subsequent operation should only be initiated after t mrd . violating these requirements will result in unspe cified opera- tion. the extended mode register is written by asserting low on cs , ras , cas , we and high on ba0. the state of address pins a0 ~ a12 and ba1 in the same cycle as cs , ras , cas and we going low are written in the extended mode regis- ter. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the con- troller must wait the specified time before initiat ing any subsequent operation. violating either of t hese requirements will result in unspecified operation. this register includes the selection of partial arr ay to be refreshed (full array, half array, quarter array, etc.). the extended mode register set must be done before any activate command after the power up sequence. any c ontents of the mode register be altered by re-programming the mode register through the execution of extended mod e register set command. partial array self refresh (pasr) with pasr, the self refresh may be restricted to a variable portion of the total array. the whole arra y (default), 1/2 array, 1/4 array, 1/8 array or 1/16 array could be selected. drive strength (ds) the drive strength could be set to full or half via address bits a5 and a6. the half drive strength is intended for lighter loads or point-to-point environments.
rev 1.2 / july. 2009 54 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series status register read the status register contains the specific die infor mation such as density, device type, data bus width , refresh rate, revision id and manufacturers. the status register is only for read. below figure is status register r ead timing dia- gram. to read out the status register values, ba[1:0] set to 01b and a[12:0] set to all 0 with mrs command f ollowed by read command with that ba[1:0] and a[12:0] are don t care. note) 1. srr can only be issued after power-up sequence i s complete. 2. srr can only be issued with all banks precharged . 3. srr cl is unchanged from value in the mode regis ter. 4. srr bl is fixed at 2. 5. tsrr = 2 clk (min) 6. tsrc = cl + 1. (min time between read to next va lid command) 7. no commands other than nop and deselect are allo wed between the srr and the read. cmd tck trp tsrr nop mrs nop read nop nop nop cmd register value out tsrc clk clk cmd ba[1:0] add dqs dq[15:0] 01 0 cl = 3 don t care pre all or pre
rev 1.2 / july. 2009 55 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series power down power down occurs if cke is set low coincident with device deselect or nop command and when no accesse s are in progress. if power down occurs when all banks are i dle, it is precharge power down. if power down occurs when one or more banks are act ive, it is referred to as active power down. the de vice cannot stay in this mode for longer than the refresh requi rements of the device, without losing data. the pow er down state is exited by setting cke high while issuing a device d eselect or nop command. a valid command can be issued after t xp . for clock stop during power down mode, please ref er to the clock stop sub- section in operation section of this datasheet. note: this case shows cke low coincident with no op eration. alternately power down entry can be achie ved with cke low coincident with device deselect. deep power down the deep power down (dpd) mode enables very low sta ndby currents. all internal voltage generators insi de the mobile ddr sdram are stopped and all memory data is lost in this mode. all the information in the mode register and the ex tended mode register is lost. next figure, deep power down command shows the deep power down command all banks must b e in idle state with no activity on the data bus prior to entering the dpd mode. while in this state , cke must be held in a constant low state. to exit the dpd mode, cke is taken high after the c lock is stable and nop command must be maintained f or at least 200 us. after 200 us a complete re-initialization r outing is required following steps 4 through 11 as defined in power- up and initialization sequences. dpd is an optional feature, so please contact hynix office for the dp d feature. don't care don't care deep power down entry command power-down entry command cs a0~a12 we cas clk clk cke ba0, ba1 ras cs a0~a12 we cas clk clk cke ba0, ba1 ras
rev 1.2 / july. 2009 56 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series mobile ddr sdram deep power down entry and exit before entering deep power down the dram must be in an all banks idle state with no activity on the da ta bus. upon entering deep power down all data will be lost. whi le in deep power down cke must be held in a constan t low state. upon exiting deep power down nop command must be ma intained for 200us. after 200us a complete initiali zation routine is required following steps 4 through 11 as defined in power-up and initialization sequences. mobile ddr sdram deep power-down entry and exit note: 1. clock must be stable before exiting deep power d own mode. that is, the clock must be cycling within specifications by ta0. 2. device must be in the all banks idle state prior to entering deep power down mode. 3. 200us is required before any command can be appl ied upon exiting dpd. 4. dpd = deep power down command. 5. upon exiting deep power down a precharge all com mand must be issued followed by two auto refresh co mmands and a load mode register sequence. don't care nop dpd 4 nop valid 5 valid t 0 t 1 ta0 1 ta 1 tb 1 tck tih tis tch tcl tis tih tis tih tis trp 2 deep power down mode exit deep power down mode t=200us 3 ck ck cke com add dqs dq dm tis
rev 1.2 / july. 2009 57 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series cas latency definition cas latency definition of mobile ddr sdram must be must be loaded when all banks are idle, and the con troller must wait the specified time before initiating the subse quent operation. cas latency definition: with cl = 3 the first data element is valid at (2 * t ck + t ac ) after the clock at which the read command was registered (see figure 2) cas latency definition note 1. dq transitioning after dqs transition de fine t dqsq window. 2. all dq must transition by t dqsq after dqs transitions, regardless of tac. 3. tac is the dq output window relative to ck, and is the long term component of dq skew. read nop nop nop nop t 0 t 1 t 3 t 4 t 5 t 2 t 2n t 3n t 4n t 5n t 6 nop nop t 2 t 2n t 3 t 3n t 4 t 4n t 5 t 5n all dq values, collectively 2 cl = 3 tlz trpre tlz tdqsck tdqsck trpst dqs cmd ck ck tac tdqsq
rev 1.2 / july. 2009 58 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series clock stop mode clock stop mode is a feature supported by mobile dd r sdram devices. it reduces clock-related power con sumption during idle periods of the device. conditions: the mobile ddr sdram supports clock sto p in case: the last access command (active, read, write, prec harge, auto refresh or mode register set) has executed to completion, including any data-out duri ng read bursts; the number of required clock pulses per access command depends on the device's ac timing parameter s and the clock frequency; the related timing condition (t rcd , t wr , t rp , t rfc , t mrd ) has been met; cke is held high. when all conditions have been met, the device is ei ther in ''idle'' or ''row active'' state, and clock stop mode may be entered with ck held low and ck held high. clock stop mode is exited when the cloc k is restarted. nops command have to be issued for at least one clock cycle befo re the next access command may be applied. addition al clock pulses might be required depending on the system character istics. figure1 illustrates the clock stop mode: initially the device is in clock stop mode; the clock is restarted with the rising edge of t0 and a nop on the command inputs; with t 1 a valid access command is latched; this command is followed by nop commands in order to allow for clo ck stop as soon as this access command has completed; t n is the last clock pulse required by the access com mand latched with t 1. the timing condition of this access command is met with the completion of t n ; therefore tn is the last clock pulse required by this command and the clock is then stop ped. clock stop mode ck add cmd nop nop nop nop valid clock stopped exit clock stop mode valid command enter clock stop mode don't care (high-z) ck cm d t 0 t 1 t 2 t n cke dq, dqs timing condition
rev 1.2 / july. 2009 59 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series data mask 1,2) mobile ddr sdram uses a dq write mask enable signal (dm) which masks write data. data masking is only available in the write cycle f or mobile ddr sdram. data masking is available duri ng write, but data masking during read is not available. dm command masks burst write data with reference to data strobe signal and it is not related with read data. dm com- mand can be initiated at both the rising edge and t he falling edge of the dqs. dm latency for write op eration is zero. for x16 data i/o, mobile ddr sdram is equipped with ldm and udm which control dq0~dq7 and dq8~dq15 respectively. note: 1) mobile sdr sdram can mask both read and write da ta, but the read mask is not supported by mobile dd r sdram. 2) differences in functions and specifications (nex t table) data masking (write cycle: bl=4) item mobile ddr sdram mobile sdr sdram data mask write mask only write mask/read mask write write dm cmd ck ck d0 d1 d3 d0 d1 d3 hi- z dqs dq data masking data masking tdqss tdqsl tds tdh tdqsh hi- z
rev 1.2 / july. 2009 60 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series power-up and initialization sequences mobile ddr sdram must be powered up and initialized in a predefined manner. operations procedures othe r thank those specified may result in undefined operation. if there is any interruption to the device power, t he initialization routine should be followed. the steps to be followe d for device initialization are listed below. step1: provide power, the device core power (v dd ) and the device i/o power (v ddq ) must be brought up simulta- neously to prevent device latch-up. although not re quired, it is recommended that v dd and v ddq are from the same power source. also assert and hold clock e nable (cke) to a lvcmos logic high level. step 2: once the system has established consistent device power and cke is driven high, it is safe to apply stable clock. step 3: there must be at least 200us of valid clock s before any command may be given to the dram. duri ng this time nop or deselect commands must be issued on the command bus. step 4: issue a precharge all command. step 5: provide nops or deselect commands for at le ast t rp time. step 6: issue an auto refresh command followed by n ops or deselect command for at least t rfc time. issue the second auto refresh command followed by nops or deselect command for at least t rfc time. note as part of the initialization sequence there must be two auto refresh commands is sued. the typical flow is to issue them at step 6, but they may also be issued between steps 10 and 11. step 7: using the mrs command, load the base mode r egister. set the desired operating modes. step 8: provide nops or deselect commands for at le ast t mrd time. step 9: using the mrs command, program the extended mode register for the desired operating modes. not e the order of the base and extended mode register progra mming is not important. step 10: provide nop or deselct commands for at lea st t mrd time. step 11: the dram has been properly initialized and is ready for any valid command.
rev 1.2 / july. 2009 61 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series the initialization flow sequence is below. initialization waveform sequence vdd vddq /clk clk cke cmd dm addr a10 ba0, ba1 dq, dqs t=200usec trp tmrd trfc tmrd vdd/vddq powered up clock stable auto refresh nop arf pre mrs arf act mrs code ra code code ra code ba0=l ba1=l ba ba0=l ba1=h trfc load mode register tch tcl tck all banks tis tih tis tih tis tih tis tih don't care high-z precharge all auto refresh load extended mode register
rev 1.2 / july. 2009 62 mobile ddr sdram 256mbit (16m x 16bit) h5ms2562jfr series package information 60 ball fbga 0.8mm pitch [8.0mm x 10.0 mm, t=1.0mm max] unit [mm] 0.8 bottom view 0.340 +/-0.05 0.80 typ. 0.80 typ. 1.00 max 3.20 1.60 0.450 +/- 0.05 a1 index mark 1.375 10.00 typ. 1.40 8 . 00 typ .

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